1. Field of the Invention
Example embodiments relate to a semiconductor memory device. More particularly, example embodiments relate to a NAND flash memory device having a contact for controlling a well potential.
2. Description of the Related Art
Flash memory devices are non-volatile memory devices that can retain stored data regardless of power supply. Conventional flash memory devices may be classified into NOR flash memory devices and NAND flash memory devices depending on a connection structure of their respective memory cells with a bit line and a source line.
A conventional NAND flash memory device may include a plurality of memory cells connected in series between bit lines and a common source line, and each of the memory cells may be connected to a respective word line via a gate electrode. The conventional NAND flash memory device may be manufactured, e.g., by a double patterning process, to provide a high integration degree, e.g., a NAND flash memory device formed according to a reduced design rule with minimized pitch in order to decrease a chip size.
Manufacturing of the conventional NAND flash memory device according to a reduced design rule, however, may be difficult to realize with the existing exposure equipment and exposure technology, e.g., existing lithography technology. For example, using the double patterning process to manufacture the NAND flash memory device may include formation of a plurality of periodic patterns with a fine pitch, followed by removal of a portion of the fine patterns from a predetermined region, i.e., a trimming process, to isolate predetermined fine patterns, e.g., to form contacts. The trimming process of fine patterns, however, may be complex and beyond the existing lithography technology.
For example, since a NAND flash memory device according to a reduced design rule may include a device isolation layer defining a plurality of active regions, e.g., a plurality of fine line patterns, isolation of predetermined fine line patterns to form contacts, i.e., a plurality of fine island patterns, may require a complex mask layout to account for a non-uniform shape of the active region, e.g., due to different patterns of the active regions in the NAND flash memory device. Use of a complex layout for trimming may increase manufacturing time and costs, and may decrease reliability and manufacturing yield of the conventional NAND flash memory device.